双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVCH16374DL

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此产品已停产

Alternatives

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE™ flow-through standard pin-out architecture

  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold

  • Latch-up performance exceeds 100 mA per JESD 78 Class II.A

  • Output drive capability 50 Ω transmission lines at 85 °C

  • IOFF circuitry provides partial Power-down mode operation

  • Current drive ±24 mA at VCC = 3.0 V

  • Complies with JEDEC standards:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:
    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C

参数类型

型号 Package name
74ALVCH16374DL SSOP48

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVCH16374DL 74ALVCH16374DL,112
(935260444112)		 Obsolete ALVCH16374 Standard Procedure Standard Procedure SOT370-1
SSOP48
(SOT370-1) 		SOT370-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暂无信息
74ALVCH16374DL,118
(935260444118)		 Obsolete ALVCH16374 Standard Procedure Standard Procedure SOT370-1_118

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVCH16374DL 74ALVCH16374DL,112 74ALVCH16374DL rohs rhf rhf
74ALVCH16374DL 74ALVCH16374DL,118 74ALVCH16374DL rohs rhf rhf
品质及可靠性免责声明

Series

文档 (6)

文件名称 标题 类型 日期
74ALVCH16374 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state Data sheet 2024-06-19
alvch16374 alvch16374 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT370-1 plastic, shrink small outline package; 48 leads; 0.635 mm pitch; 15.9 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
alvch16374 alvch16374 IBIS model IBIS model 2013-04-08

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