双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVCH16821DL

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable nOE control gates.

Each register is fully edge triggered. The state of each nDn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s nQn output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

此产品已停产

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low-power consumption

  • Direct interface with TTL levels

  • Current drive ± 24 mA at 3.0 V

  • MULTIBYTE™ flow-through standard pin-out architecture

  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce

  • Output drive capability 50 Ω transmission lines at 85°C

  • All data inputs have bushold

  • Complies with JEDEC standard no. 8-1A

  • Complies with JEDEC standards:

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8B/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C

参数类型

型号 Package name
74ALVCH16821DL SSOP56

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVCH16821DL 74ALVCH16821DL,112
(935259000112)		 Obsolete ALVCH16821 Standard Procedure Standard Procedure SOT371-1
SSOP56
(SOT371-1) 		SOT371-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暂无信息
74ALVCH16821DL,118
(935259000118)		 Obsolete ALVCH16821 Standard Procedure Standard Procedure 暂无信息
74ALVCH16821DL,512
(935259000512)		 Obsolete ALVCH16821 Standard Procedure Standard Procedure 暂无信息
74ALVCH16821DL,518
(935259000518)		 Obsolete ALVCH16821 Standard Procedure Standard Procedure 暂无信息

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVCH16821DL 74ALVCH16821DL,112 74ALVCH16821DL rohs rhf rhf
74ALVCH16821DL 74ALVCH16821DL,118 74ALVCH16821DL rohs rhf rhf
74ALVCH16821DL 74ALVCH16821DL,512 74ALVCH16821DL rohs rhf rhf
74ALVCH16821DL 74ALVCH16821DL,518 74ALVCH16821DL rohs rhf rhf
品质及可靠性免责声明

Series

文档 (6)

文件名称 标题 类型 日期
74ALVCH16821 20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state Data sheet 2024-07-09
alvch16821 alvch16821 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT371-1 plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

模型

文件名称 标题 类型 日期
alvch16821 alvch16821 IBIS model IBIS model 2013-04-08

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册