可订购部件
| 型号 | 可订购的器件编号 | 订购代码(12NC) | 封装 | 从经销商处购买 |
|---|---|---|---|---|
| 74HC109D-Q100 | 74HC109D-Q100J | 935334221118 | SOT109-1 | 订单产品 |
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Click here for more information74HC109D-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
J and K inputs for easy D-type flip-flop
Toggle flip-flop or "do nothing" mode
Wide supply voltage range:
For 74HC109-Q100: from 2.0 V to 6.0 V
For 74HCT109-Q100: from 4.5 V to 5.5 V
CMOS low power dissipation
High noise immunity
Input levels:
For 74HC109-Q100: CMOS level
For 74HCT109-Q100: TTL level
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
74HC109-Q100 complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
74HCT109-Q100 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
参数类型
| 型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74HC109D-Q100 | 2.0 - 6.0 | CMOS | ± 5.2 | 15 | 75 | low | -40~125 | SO16 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74HC109D-Q100 | 74HC109D-Q100J (935334221118) |
Active | 74HC109D |
SO16 (SOT109-1) |
SOT109-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT109-1_118 |
Series
文档 (12)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74HC_HCT109_Q100 | Dual JK flip-flop with set and reset; positive-edge-trigger | Data sheet | 2024-02-21 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| SOT109-1 | 3D model for products with SOT109-1 package | Design support | 2020-01-22 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SO16_SOT109-1_mk | plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.35 mm body | Marcom graphics | 2017-01-28 |
| SOT109-1 | plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm body | Package information | 2023-11-07 |
| SOT109-1_118 | SO16; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2024-02-19 |
| 74HC109D-Q100_Nexperia_Product_Reliability | 74HC109D-Q100 Nexperia Product Reliability | Quality document | 2024-06-16 |
| SO-SOJ-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SO-SOJ-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
| WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
支持
如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。
模型
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| SOT109-1 | 3D model for products with SOT109-1 package | Design support | 2020-01-22 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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订购、定价与供货
| 型号 | Orderable part number | Ordering code (12NC) | 状态 | 包装 | Packing Quantity | 在线购买 |
|---|---|---|---|---|---|---|
| 74HC109D-Q100 | 74HC109D-Q100J | 935334221118 | Active | SOT109-1_118 | 2,500 | 订单产品 |
样品
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如果您没有 Nexperia 的直接账户，我们的全球和地区分销商网络可为您提供 Nexperia 样品支持。查看官方经销商列表。
How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74HC109D-Q100
Dual JK flip-flop with set and reset; positive-edge-trigger
从安世半导体购买
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