可订购部件
| 型号 | 可订购的器件编号 | 订购代码(12NC) | 封装 | 从经销商处购买 |
|---|---|---|---|---|
| 74LVC16374ADGG | 74LVC16374ADGG,118 | 935235190118 | SOT362-1 | 订单产品 |
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Click here for more information74LVC16374ADGG
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
The 74LVC16374A; 74LVCH16374A is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
Multibyte flow-through standard pinout architecture
Low inductance multiple supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16374A only)
High-impedance outputs when VCC = 0 V
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
参数类型
| 型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|
| 74LVC16374ADGG | 1.2 - 3.6 | CMOS/LVTTL | ± 24 | 3.8 | 150 | low | -40~125 | TSSOP48 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
|---|---|
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封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74LVC16374ADGG | 74LVC16374ADGG,118 (935235190118) |
Active | LVC16374A |
TSSOP48 (SOT362-1) |
SOT362-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT362-1_118 |
Series
文档 (11)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74LVC_LVCH16374A | 16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state | Data sheet | 2024-04-22 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
| SOT362-1 | 3D model for products with SOT362-1 package | Design support | 2020-01-22 |
| lvc16374a | lvc16374a IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP48_SOT362-1_mk | plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body | Marcom graphics | 2017-01-28 |
| SOT362-1 | plastic thin shrink small outline package; 48 leads; body width 6.1 mm | Package information | 2024-01-05 |
| SOT362-1_118 | TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74LVC16374ADGG_Nexperia_Product_Reliability | 74LVC16374ADGG Nexperia Product Reliability | Quality document | 2024-06-16 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
订购、定价与供货
| 型号 | Orderable part number | Ordering code (12NC) | 状态 | 包装 | Packing Quantity | 在线购买 |
|---|---|---|---|---|---|---|
| 74LVC16374ADGG | 74LVC16374ADGG,118 | 935235190118 | Active | SOT362-1_118 | 2,000 | 订单产品 |
样品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74LVC16374ADGG
16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
从安世半导体购买
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