双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC2G00GS

Dual 2-input NAND gate

The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant outputs for interfacing with 5 V logic

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Overvoltage tolerant inputs to 5.5 V

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74LVC2G00GS 1.65 - 5.5 CMOS/LVTTL ± 32 2.2 175 2 low -40~125 XSON8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC2G00GS 74LVC2G00GS,115
(935292381115)		 Active VA SOT1203
XSON8
(SOT1203) 		SOT1203 REFLOW_BG-BD-1
SOT1203_115

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC2G00GS 74LVC2G00GS,115 74LVC2G00GS rohs rhf rhf
品质及可靠性免责声明

Series

文档 (12)

文件名称 标题 类型 日期
74LVC2G00 Dual 2-input NAND gate Data sheet 2024-05-08
AN11009 Pin FMEA for LVC family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT1203 3D model for products with SOT1203 package Design support 2023-02-02
lvc2g00 74LVC2G00 IBIS model IBIS model 2014-10-20
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
XSON8_SOT1203_mk plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body Marcom graphics 2019-02-04
SOT1203 plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body Package information 2022-06-03
SOT1203_115 XSON8; Reel pack for SMD, 7''; Q1/T1 product orientation Packing information 2020-04-21
74LVC2G00GS_Nexperia_Product_Reliability 74LVC2G00GS Nexperia Product Reliability Quality document 2024-06-16
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT1203 MAR_SOT1203 Topmark Top marking 2013-06-03

支持

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模型

文件名称 标题 类型 日期
lvc2g00 74LVC2G00 IBIS model IBIS model 2014-10-20
SOT1203 3D model for products with SOT1203 package Design support 2023-02-02

PCB Symbol, Footprint and 3D Model

Model Name 描述

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74LVC2G00GS 74LVC2G00GS,115 935292381115 Active SOT1203_115 5,000 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC2G00GS 74LVC2G00GS,115 935292381115 SOT1203 订单产品