双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC374ADB

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

The 74LVC374A is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

此产品已停产

Alternatives

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • 8-bit positive edge-triggered register

  • Independent register and 3-state buffer operation

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 Package name
74LVC374ADB SSOP20

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC374ADB 74LVC374ADB,112
(935218670112)		 Obsolete LVC374A SOT339-1
SSOP20
(SOT339-1) 		SOT339-1 SSOP-TSSOP-VSO-WAVE
暂无信息
74LVC374ADB,118
(935218670118)		 Obsolete LVC374A SOT339-1_118
74LVC374ADB/G,118
(935277672118)		 Obsolete LVC374A Standard Procedure Standard Procedure SOT339-1_118

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC374ADB 74LVC374ADB,112 74LVC374ADB rohs rhf rhf
74LVC374ADB 74LVC374ADB,118 74LVC374ADB rohs rhf rhf
74LVC374ADB 74LVC374ADB/G,118 74LVC374ADB rohs rhf rhf
品质及可靠性免责声明

Series

文档 (8)

文件名称 标题 类型 日期
74LVC374A Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state Data sheet 2023-09-01
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
lvc374a lvc374a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT339-1 plastic, shrink small outline package; 20 leads; 0.65 mm pitch; 7.2 mm x 5.3 mm x 2 mm body Package information 2020-04-21
lvc lvc Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

模型

文件名称 标题 类型 日期
lvc374a lvc374a IBIS model IBIS model 2013-04-09
lvc lvc Spice model SPICE model 2013-05-07

PCB Symbol, Footprint and 3D Model

Model Name 描述

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册