双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVCH16600

18-bit universal bus transceiver; 3-state

The 74ALVCH16600 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), clock enable (CEAB and CEBA) and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB and CEAB are LOW, the A-bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA, CEBA and CPBA.. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 1.65 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE™ flow-through standard pin-out architecture

  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce

  • Direct interface with TTL levels (2.7 V to 3.6 V)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Bus hold on data inputs

  • Output drive capability 50 Ω transmission lines at 85 °C

  • Current drive ±24 mA at 3.0 V

  • Complies with JEDEC standards:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsfmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Package name
74ALVCH16600DGGProductionn.a.n.a.TTL± 242.818150low-40~8593TSSOP56

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74ALVCH16600DGG
TSSOP56
(SOT364-1) 		SOT364-1SSOP-TSSOP-VSO-WAVE
SOT364-1_118ActiveALVCH1660074ALVCH16600DGG:11
( 9352 625 45118 )

停产信息

型号可订购的器件编号，（订购码(12NC)）最后一次购买日期最后一次交货日期替代产品状态备注
74ALVCH16600DGG935262545518
74ALVCH16600DGG9352625455122021-12-312022-06-3074ALVCH16600DGG
    74ALVCH16600DGG935262545112

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74ALVCH16600DGG74ALVCH16600DGG:1174ALVCH16600DGGweek 2, 2006
    品质及可靠性免责声明

    文档 (5)

    文件名称标题类型日期
    74ALVCH1660018-bit universal bus transceiver; 3-stateData sheet2024-07-04
    alvch16600alvch16600 IBIS modelIBIS model2013-04-07
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
    SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyPackage information2022-06-23

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    模型

    文件名称标题类型日期
    alvch16600alvch16600 IBIS modelIBIS model2013-04-07

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