双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVCH16821

20-bit bus-interface D-type flip-flop; positive-edge trigger; 3-state

The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable nOE control gates.

Each register is fully edge triggered. The state of each nDn input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s nQn output.

When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops.

The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

特性

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low-power consumption

  • Direct interface with TTL levels

  • Current drive ± 24 mA at 3.0 V

  • MULTIBYTE™ flow-through standard pin-out architecture

  • Low inductance multiple VCC and GND pins for minimum noise and ground bounce

  • Output drive capability 50 Ω transmission lines at 85°C

  • All data inputs have bushold

  • Complies with JEDEC standard no. 8-1A

  • Complies with JEDEC standards:

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8B/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
  • Specified from -40 °C to +85 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVCH16821DGGProduction1.2 - 3.6TTL± 242.5350low-40~859321.0TSSOP56

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74ALVCH16821DGG
TSSOP56
(SOT364-1) 		SOT364-1SSOP-TSSOP-VSO-WAVE
SOT364-1_118ActiveALVCH1682174ALVCH16821DGG,11
( 9352 590 10118 )

停产信息

型号可订购的器件编号，（订购码(12NC)）最后一次购买日期最后一次交货日期替代产品状态备注
74ALVCH16821DGG935259010518
74ALVCH16821DGG9352590105122021-12-312022-06-3074ALVCH16821DGG
    74ALVCH16821DGG935259010112

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74ALVCH16821DGG74ALVCH16821DGG,1174ALVCH16821DGGweek 2, 2006
    品质及可靠性免责声明

    文档 (5)

    文件名称标题类型日期
    74ALVCH1682120-bit bus-interface D-type flip-flop; positive-edge trigger; 3-stateData sheet2024-07-09
    alvch16821alvch16821 IBIS modelIBIS model2013-04-07
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
    SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyPackage information2022-06-23

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    模型

    文件名称标题类型日期
    alvch16821alvch16821 IBIS modelIBIS model2013-04-07

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