双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVT162823

18-bit bus-interface D-type flip-flop with reset and enable with 30 Ohm termination resistors; 3-state

The 74ALVT162823 is an 18-bit positive-edge triggered D-type flip-flop with 30 Ω termination resistors, 3-state outputs reset and enable.

The device can be used as two 9-bit flip-flops or one 18-bit flip-flop. The device features clock (nCP), clock enable (nCE), master reset (nMR) and output enable (nOE, inputs each controlling 9-bits. When nCE is LOW, the flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. A LOW on nMR will reset the flip-flops LOW. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs.

特性

  • Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops

  • 5 V I/O compatible

  • Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors

  • Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

  • Live insertion and extraction permitted

  • Power-up 3-state

  • Power-up reset

  • Output capability: +12 mA to −12 mA

  • Outputs include series resistance of 30 Ω making external termination resistors unnecessary

  • Latch-up protection:

    • JESD78: exceeds 500 mA

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74ALVT162823DGGProduction2.3 - 3.6TTL± 123.0150medium-40~859321.0TSSOP56

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74ALVT162823DGG
TSSOP56
(SOT364-1) 		SOT364-1SSOP-TSSOP-VSO-WAVE
SOT364-1_118ActiveALVT16282374ALVT162823DGG,11
( 9352 616 58118 )

下表中的版本已停产。参见表 停产信息 了解更多信息。

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74ALVT162823DGG
TSSOP56
(SOT364-1) 		SOT364-1SSOP-TSSOP-VSO-WAVE
SOT364-1_512Withdrawn / End-of-lifeALVT16282374ALVT162823DGGS
( 9352 616 58512 )

停产信息

型号可订购的器件编号，（订购码(12NC)）最后一次购买日期最后一次交货日期替代产品状态备注
74ALVT162823DGG9352616585122021-12-312022-06-3074ALVT162823DGG
    74ALVT162823DGG935261658518
    74ALVT162823DGG935261658112

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74ALVT162823DGG74ALVT162823DGG,1174ALVT162823DGGweek 2, 2006

    下表中的版本已停产。参见表 停产信息 了解更多信息。

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74ALVT162823DGG74ALVT162823DGGS74ALVT162823DGGAlways Pb-free
    品质及可靠性免责声明

    文档 (6)

    文件名称标题类型日期
    74ALVT16282318-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-stateData sheet2024-06-25
    alvt162823alvt162823 IBIS modelIBIS model2013-04-07
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    alvt16alvt16 Spice modelSPICE model2013-05-06
    SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
    SOT364-1plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm bodyPackage information2022-06-23

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    模型

    文件名称标题类型日期
    alvt162823alvt162823 IBIS modelIBIS model2013-04-07
    alvt16alvt16 Spice modelSPICE model2013-05-06

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