双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT1203

74AVC1T8832

Single dual-supply translating 2-input OR with strobe

The 74AVC1T8832 is a single dual-supply translating 2-input OR with strobe inputs. It features two data input pins (A, B), two strobe input pins (STRA, STRB), one data output pin (Y) and dual-supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A, B, STRA and STRB are referenced to VCC(A) and pin Y is referenced to VCC(B).

The logic equation provided at the Y output is:

  • Y = STRA•A + STRB•B

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In Suspend mode when either VCC(A) or VCC(B) are at GND level, the Y output is in the high-impedance OFF-state.

Features and benefits

  • Wide supply voltage range:

    • VCC(A): 0.8 V to 3.6 V

    • VCC(B): 0.8 V to 3.6 V

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 500 Mbit/s (1.8 V to 3.3 V translation)

    • 320 Mbit/s (<1.8 V to 3.3 V translation)

    • 320 Mbit/s (translate to 2.5 V or 1.8 V)

    • 280 Mbit/s (translate to 1.5 V)

    • 240 Mbit/s (translate to 1.2 V)

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AVC1T8832GS n.a. CMOS/LVTTL ± 12 2.4 1 very low -40~125 XSON8

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVC1T8832GS 74AVC1T8832GSX
(935690694115)		 Active Bf SOT1203
XSON8
(SOT1203) 		SOT1203 REFLOW_BG-BD-1
SOT1203_115

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVC1T8832GS 74AVC1T8832GSX 74AVC1T8832GS rohs rhf rhf
品质及可靠性免责声明

文档 (11)

文件名称 标题 类型 日期
74AVC1T8832 Single dual-supply translating 2-input OR with strobe Data sheet 2024-06-25
AN90007 Pin FMEA for AVC family Application note 2018-11-30
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT1203 3D model for products with SOT1203 package Design support 2023-02-02
avc1t8832 74AVC1T8832 IBIS model IBIS model 2018-10-03
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
XSON8_SOT1203_mk plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body Marcom graphics 2019-02-04
SOT1203 plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm body Package information 2022-06-03
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
MAR_SOT1203 MAR_SOT1203 Topmark Top marking 2013-06-03

支持

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模型

文件名称 标题 类型 日期
SOT1203 3D model for products with SOT1203 package Design support 2023-02-02
avc1t8832 74AVC1T8832 IBIS model IBIS model 2018-10-03

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