双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVT16652ADGG

3.3 V 16-bit bus transceiver/register; 3-state

The 74LVT16652A is a high-performance BiCMOS product designed for VCC operation at 3.3 V. The device can be used as two 8-bit transceivers or one 16-bit transceiver.

Complimentary output enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. A LOW input level selects real-time data, and a HIGH input level selects stored data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data.

Data on the A or B bus, or both, can be stored in the internal flip-flops by LOW-to-HIGH transitions at the appropriate clock (CPAB or CPBA) inputs regardless of the levels on the select control or output enable inputs. When SAB and SBA are in real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high- impedance, each set of bus lines remains at its last level configuration.

此产品已停产

Features and benefits

  • 16-bit bus interface
  • 3-state buffers
  • Output capability: +64 mA and -32 mA
  • TTL input and output switching levels
  • Input and output interface capability to systems at 5 V supply
  • Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs
  • Live insertion and extraction permitted
  • Power-up reset
  • Power-up 3-state
  • No bus current loading when output is tied to 5 V bus
  • Latch-up protection exceeds 500 mA per JESD78
  • ESD protection:
    • MIL STD 883 method 3015: exceeds 2000 V
    • Machine model: exceeds 200 V

Applications

参数类型

型号 Package name
74LVT16652ADGG TSSOP56

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号,(订购码(12NC)) 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVT16652ADGG 74LVT16652ADGG,112
(935204700112)
Obsolete LVT16652A Standard Procedure Standard Procedure SOT364-1
TSSOP56
(SOT364-1)
SOT364-1 SSOP-TSSOP-VSO-WAVE
暂无信息
74LVT16652ADGG,118
(935204700118)
Obsolete LVT16652A Standard Procedure Standard Procedure SOT364-1_118
74LVT16652ADGGS
(935204700512)
Obsolete LVT16652A Standard Procedure Standard Procedure 暂无信息
74LVT16652ADGGY
(935204700518)
Obsolete LVT16652A Standard Procedure Standard Procedure 暂无信息

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVT16652ADGG 74LVT16652ADGG,112 74LVT16652ADGG rohs rhf rhf
74LVT16652ADGG 74LVT16652ADGG,118 74LVT16652ADGG rohs rhf rhf
74LVT16652ADGG 74LVT16652ADGGS 74LVT16652ADGG rohs rhf rhf
74LVT16652ADGG 74LVT16652ADGGY 74LVT16652ADGG rohs rhf rhf
品质及可靠性免责声明

文档 (7)

文件名称 标题 类型 日期
74LVT16652A 3.3 V 16-bit bus transceiver/register; 3-state Data sheet 2005-01-11
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
lvt16652a lvt16652a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
lvt16 lvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名称 标题 类型 日期
lvt16652a lvt16652a IBIS model IBIS model 2013-04-09
lvt16 lvt16 Spice model SPICE model 2013-05-07
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.