双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AVC1T1004

1-to-4 fan-out buffer

The 74AVC1T1004 is a translating 1-to-4 fan-out buffer suitable for use in clock distribution. It has dual supplies (VCC(A) and VCC(B)) for voltage translation. It also has a data input (A), four data outputs (Yn) and an output enable input (OE). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V. It makes the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The levels of A and OE are referenced to VCC(A), outputs Yn are referenced to VCC(B). This supply configuration ensures that the fanned out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range:

    • VCC(A): 0.8 V to 3.6 V

    • VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AVC1T1004DP 0.8 - 3.6 0.8 - 3.6 CMOS/LVTTL ± 12 4.9 1 very low -40~125 TSSOP10

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVC1T1004DP 74AVC1T1004DPJ
(935690122118)		 Active Bc SOT552-1
TSSOP10
(SOT552-1) 		SOT552-1 SSOP-TSSOP-VSO-WAVE
SOT552-1_118

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVC1T1004GU33 74AVC1T1004GU33Z
(935690126471)		 Withdrawn / End-of-life Bc SOT1430-1
X2QFN10
(SOT1430-1) 		SOT1430-1 SOT1430-1_471

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVC1T1004DP 74AVC1T1004DPJ 74AVC1T1004DP rohs rhf rhf

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVC1T1004GU33 74AVC1T1004GU33Z 74AVC1T1004GU33 rohs rhf rhf
品质及可靠性免责声明

文档 (10)

文件名称 标题 类型 日期
74AVC1T1004 1-to-4 fan-out buffer Data sheet 2024-06-25
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT552-1 3D model for products with SOT552-1 package Design support 2020-01-22
avc1t1004 74AVC1T1004 IBIS model IBIS model 2018-06-18
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP10_SOT552_mk plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT552-1 plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body Package information 2022-06-07
SOT1430-1 plastic, leadless extremely thin small outline package; 10 terminals; body 1.6 x 1.3 x 0.33 mm Package information 2020-04-21
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名称 标题 类型 日期
SOT552-1 3D model for products with SOT552-1 package Design support 2020-01-22
avc1t1004 74AVC1T1004 IBIS model IBIS model 2018-06-18

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