双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC1G38-Q100

2-input NAND gate; open drain

The 74LVC1G38-Q100 is a single 2-input NAND gate with open-drain output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant outputs for interfacing with 5 V logic

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Open drain outputs

  • Direct interface with TTL levels

  • Inputs accept voltages up to 5 V

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V).

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74LVC1G38GV-Q100 1.65 - 5.5 CMOS/LVTTL 32 2.3 175 1 low -40~125 TSOP5
74LVC1G38GW-Q100 1.65 - 5.5 CMOS/LVTTL 32 2.3 175 1 low -40~125 TSSOP5

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC1G38GV-Q100 74LVC1G38GV-Q100H
(935302104125)		 Active YB SOT753
TSOP5
(SOT753) 		SOT753 REFLOW_BG-BD-1
WAVE_BG-BD-1
SOT753_125
74LVC1G38GW-Q100 74LVC1G38GW-Q100H
(935302105125)		 Active YB SOT353-1
TSSOP5
(SOT353-1) 		SOT353-1 WAVE_BG-BD-1
SOT353-1_125

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC1G38GV-Q100 74LVC1G38GV-Q100H 74LVC1G38GV-Q100 rohs rhf rhf
74LVC1G38GW-Q100 74LVC1G38GW-Q100H 74LVC1G38GW-Q100 rohs rhf rhf
品质及可靠性免责声明

文档 (14)

文件名称 标题 类型 日期
74LVC1G38_Q100 2-input NAND gate; open drain Data sheet 2023-08-18
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT753 3D model for products with SOT753 package Design support 2019-01-22
SOT353-1 3D model for products with SOT353-1 package Design support 2019-09-23
lvc1g38 74LVC1G38 IBIS model IBIS model 2014-10-20
Nexperia_document_leaflet_Logic_X2SON_packages_062018 X2SON ultra-small 4, 5, 6 & 8-pin leadless packages Leaflet 2018-06-05
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP5_SOT353-1_mk plastic, thin shrink small outline package; 5 leads; 0.65 mm pitch; 2 mm x 1.25 mm x 0.95 mm body Marcom graphics 2018-07-25
SOT753 plastic, surface-mounted package; 5 leads; 0.95 mm pitch; 2.9 mm x 1.5 mm x 1 mm body Package information 2022-05-31
SOT353-1 plastic thin shrink small outline package; 5 leads; body width 1.25 mm Package information 2022-11-15
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
MAR_SOT753 MAR_SOT753 Topmark Top marking 2013-06-03
WAVE_BG-BD-1 Wave soldering profile Wave soldering 2021-09-08

支持

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模型

文件名称 标题 类型 日期
SOT753 3D model for products with SOT753 package Design support 2019-01-22
SOT353-1 3D model for products with SOT353-1 package Design support 2019-09-23
lvc1g38 74LVC1G38 IBIS model IBIS model 2014-10-20

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