双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AUP1G74GX

Low-power D-type flip-flop with set and reset; positive-edge trigger

The 74AUP1G74 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Overvoltage tolerant inputs to 3.6 V

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Power dissipation considerations Tamb (°C) Package name
74AUP1G74GX 0.8 - 3.6 CMOS ± 1.9 9.2 400 ultra low -40~125 X2SON8

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AUP1G74GX 74AUP1G74GXX
(935308441115)		 Active 54 SOT1233-2
X2SON8
(SOT1233-2) 		SOT1233-2 SOT1233-2_115

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AUP1G74GX 74AUP1G74GXX 74AUP1G74GX rohs rhf rhf
品质及可靠性免责声明

Series

文档 (8)

文件名称 标题 类型 日期
74AUP1G74 Low-power D-type flip-flop with set and reset; positive-edge trigger Data sheet 2024-08-09
SOT1233-2 3D model for products with SOT1233-2 package Design support 2021-01-28
aup1g74 aup1g74 IBIS model IBIS model 2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_document_leaflet_Logic_X2SON_packages_062018 X2SON ultra-small 4, 5, 6 & 8-pin leadless packages Leaflet 2018-06-05
SOT1233-2 plastic thermal enhanced extremely thin small outline package; no leads;8 terminals; body 1.35 x 0.8 x 0.32 mm Package information 2022-04-21
SOT1233-2_115 X2SON8; Reel pack for SMD, 7''; Q1/T1 product orientation Packing information 2020-05-12
74AUP1G74GX_Nexperia_Product_Reliability 74AUP1G74GX Nexperia Product Reliability Quality document 2024-06-16

支持

如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

模型

文件名称 标题 类型 日期
aup1g74 aup1g74 IBIS model IBIS model 2013-04-07
SOT1233-2 3D model for products with SOT1233-2 package Design support 2021-01-28

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74AUP1G74GX 74AUP1G74GXX 935308441115 Active SOT1233-2_115 10,000 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74AUP1G74GX 74AUP1G74GXX 935308441115 SOT1233-2 订单产品