双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AUP2G32DC

Low-power dual 2-input OR gate

The 74AUP2G32 is a dual 2-input OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • CMOS low power dissipation

  • High noise immunity

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP2G32DC 0.8 - 3.6 CMOS ± 1.9 7.9 70 2 ultra low -40~125 VSSOP8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AUP2G32DC 74AUP2G32DC,125
(935280713125)		 Active p32 SOT765-1
VSSOP8
(SOT765-1) 		SOT765-1 SOT765-1_125

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AUP2G32DC 74AUP2G32DC,125 74AUP2G32DC rohs rhf rhf
品质及可靠性免责声明

Series

文档 (12)

文件名称 标题 类型 日期
74AUP2G32 Low-power dual 2-input OR gate Data sheet 2024-08-12
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11052 Pin FMEA for AUP family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT765-1 3D model for products with SOT765-1 package Design support 2020-01-22
aup2g32 aup2g32 IBIS model IBIS model 2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
VSSOP8_SOT765-1_mk plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body Marcom graphics 2017-01-28
SOT765-1 plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body Package information 2022-06-03
SOT765-1_125 VSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74AUP2G32DC_Nexperia_Product_Reliability 74AUP2G32DC Nexperia Product Reliability Quality document 2024-06-16

支持

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模型

文件名称 标题 类型 日期
aup2g32 aup2g32 IBIS model IBIS model 2013-04-07
SOT765-1 3D model for products with SOT765-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74AUP2G32DC 74AUP2G32DC,125 935280713125 Active SOT765-1_125 3,000 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74AUP2G32DC 74AUP2G32DC,125 935280713125 SOT765-1 订单产品