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Click here for more information74AUP2T1326GF
Low-power dual supply buffer/line driver; 3-state
The 74AUP2T1326 is a high-performance, dual supply, low-power, low-voltage, dual buffer/line driver with output enable circuitry.
The 74AUP2T1326 is designed for logic-level translation and combines the functions of the 74AUP1G32 and 74AUP2G126. The buffer/line driver is controlled by two output enable inputs (1OE and 2OE). A logic LOW on input 1OE causes the output 2Y to assume a high-impedance OFF-state, a logic LOW on 2OE causes the output 3Y to assume a high-impedance OFF-state. The output 1Y is the result of a logic OR of the two output enable inputs.
The output enable inputs (1OE and 2OE) are Schmitt trigger inputs, they switch at different voltages for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH. The output enable inputs accept standard input signals and are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals
Both VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced to VCC(A) and pins A, 2Y and 3Y are referenced to VCC(B).
The device ensures low static and dynamic power consumption and is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the outputs, preventing any damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range:
VCC(A): 1.1 V to 3.6 V; VCC(B): 1.1 V to 3.6 V.
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F Class 2A exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; ICC = 0.9 uA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C
Applications
参数类型
| 型号 | Package name |
|---|---|
| 74AUP2T1326GF | XSON10U |
封装
下表中的所有产品型号均已停产 。
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74AUP2T1326GF | 74AUP2T1326GF,115 (935286883115) |
Obsolete | pf | no package information | |||
| 74AUP2T1326GF,132 (935286883132) |
Obsolete | pf | |||||
环境信息
下表中的所有产品型号均已停产 。
| 型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74AUP2T1326GF | 74AUP2T1326GF,115 | 74AUP2T1326GF |
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| 74AUP2T1326GF | 74AUP2T1326GF,132 | 74AUP2T1326GF |
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Series
文档 (4)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74AUP2T1326 | low-power dual supply buffer/line driver; 3-state | Data sheet | 2017-05-03 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| Nexperia_document_Logic_CombinationLogic_infocard_201710 | Combination logic solutions card | Leaflet | 2019-08-09 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
支持
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模型
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How does it work?
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