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Click here for more information74HCT193DB
Presettable synchronous 4-bit binary up/down counter
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
For 74HC193: CMOS level
For 74HCT193: TTL level
Synchronous reversible 4-bit binary counting
Asynchronous parallel load
Asynchronous reset
Expandable without external logic
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C.
PCB Symbol, Footprint and 3D Model
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封装
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
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74HCT193DB | 74HCT193DB,112 (935189730112) |
Obsolete | no package information | ||||
74HCT193DB,118 (935189730118) |
Obsolete |
环境信息
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
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74HCT193DB | 74HCT193DB,112 | 74HCT193DB |
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74HCT193DB | 74HCT193DB,118 | 74HCT193DB |
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Series
文档 (3)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74HC_HCT193 | Presettable synchronous 4-bit binary up/down counter | Data sheet | 2024-03-14 |
AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
支持
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模型
No documents available
PCB Symbol, Footprint and 3D Model
Model Name | 描述 |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.