可订购部件
型号 | 可订购的器件编号 | 订购代码(12NC) | 封装 | 从经销商处购买 |
---|---|---|---|---|
74LV164PW-Q100 | 74LV164PW-Q100J | 935300901118 | SOT402-1 | 订单产品 |
Register once, drag and drop ECAD models into your CAD tool and speed up your design.
Click here for more information8-bit serial-in/parallel-out shift register
The 74LV164-Q100 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (DSA or DSB) and either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into Q0, which is the logical AND-function of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low-voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 °C
Gated serial data inputs
Asynchronous master reset
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|---|
74LV164PW-Q100 | 1.0 - 5.5 | TTL | ± 12 | 12 | 78 | low | -40~125 | 128 | 3.6 | 53.1 | TSSOP14 |
Model Name | 描述 |
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型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74LV164PW-Q100 | 74LV164PW-Q100J (935300901118) |
Active | LV164 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
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SOT402-1_118 |
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74LV164_Q100 | 8-bit serial-in/parallel-out shift register | Data sheet | 2024-01-31 |
SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
74lv164 | 74LV164 IBIS model | IBIS model | 2017-10-21 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
SOT402-1_118 | TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2020-04-21 |
74LV164PW-Q100_Nexperia_Product_Reliability | 74LV164PW-Q100 Nexperia Product Reliability | Quality document | 2024-06-16 |
SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
型号 | Orderable part number | Ordering code (12NC) | 状态 | 包装 | Packing Quantity | 在线购买 |
---|---|---|---|---|---|---|
74LV164PW-Q100 | 74LV164PW-Q100J | 935300901118 | Active | SOT402-1_118 | 2,500 | 订单产品 |
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The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.