双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC573APW

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Alternatives

Features and benefits

  • Wide supply voltage range from 1.2 to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • CMOS low power consumption

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • High-impedance when VCC = 0 V

  • Flow-through pinout architecture

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LVC573APW 1.2 - 3.6 TTL ± 24 3.4 low -40~125 101 4.7 45 TSSOP20

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC573APW 74LVC573APW,118
(935219020118)		 Active LVC573A LVC573A Standard Procedure Standard Procedure SOT360-1
TSSOP20
(SOT360-1) 		SOT360-1 SSOP-TSSOP-VSO-WAVE
SOT360-1_118

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC573APW 74LVC573APW,112
(935219020112)		 Withdrawn / End-of-life LVC573A LVC573A Standard Procedure Standard Procedure SOT360-1
TSSOP20
(SOT360-1) 		SOT360-1 SSOP-TSSOP-VSO-WAVE
暂无信息

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC573APW 74LVC573APW,118 74LVC573APW rohs rhf rhf

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC573APW 74LVC573APW,112 74LVC573APW rohs rhf rhf
品质及可靠性免责声明

Series

文档 (12)

文件名称 标题 类型 日期
74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Data sheet 2023-09-07
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
SOT360-1 3D model for products with SOT360-1 package Design support 2020-01-22
lvc573a lvc573a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP20_SOT360-1_mk plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT360-1 plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body Package information 2024-11-15
SOT360-1_118 TSSOP20; Reel pack for SMD, 13''; Q1/T1 product orientation Packing information 2023-08-30
74LVC573APW_Nexperia_Product_Reliability 74LVC573APW Nexperia Product Reliability Quality document 2024-06-16
lvc lvc Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名称 标题 类型 日期
lvc573a lvc573a IBIS model IBIS model 2013-04-09
lvc lvc Spice model SPICE model 2013-05-07
SOT360-1 3D model for products with SOT360-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74LVC573APW 74LVC573APW,118 935219020118 Active SOT360-1_118 2,500 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC573APW 74LVC573APW,118 935219020118 SOT360-1 订单产品