可订购部件
型号 | 可订购的器件编号 | 订购代码(12NC) | 封装 | 从经销商处购买 |
---|---|---|---|---|
74LVT573PW | 74LVT573PW,118 | 935176360118 | SOT360-1 | 订单产品 |
Register once, drag and drop ECAD models into your CAD tool and speed up your design.
Click here for more information3.3 V octal D-type transparent latch; 3-state
The 74LVT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs
Wide supply voltage range from 2.7 to 3.6 V
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
Overvoltage tolerant inputs to 5.5 V
BiCMOS high speed and output drive
Direct interface with TTL levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 500 mA per JESD 78 Class II Level B
Complies with JEDEC standard JESD8C (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C
型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|
74LVT573PW | 2.7 - 3.6 | TTL | -32/+64 | 2.7 | medium | -40~85 | 100 | 4.5 | 44 | TSSOP20 |
Model Name | 描述 |
---|---|
|
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74LVT573PW | 74LVT573PW,118 (935176360118) |
Active | LVT573 |
TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT360-1_118 |
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74LVT573 | 3.3 V octal D-type transparent latch; 3-state | Data sheet | 2024-06-07 |
SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
lvt573 | lvt573 IBIS model | IBIS model | 2013-04-09 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.2 mm body | Package information | 2024-11-15 |
SOT360-1_118 | TSSOP20; Reel pack for SMD, 13''; Q1/T1 product orientation | Packing information | 2023-08-30 |
74LVT573PW_Nexperia_Product_Reliability | 74LVT573PW Nexperia Product Reliability | Quality document | 2024-06-16 |
lvt | lvt Spice model | SPICE model | 2013-05-07 |
SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
型号 | Orderable part number | Ordering code (12NC) | 状态 | 包装 | Packing Quantity | 在线购买 |
---|---|---|---|---|---|---|
74LVT573PW | 74LVT573PW,118 | 935176360118 | Active | SOT360-1_118 | 2,500 | 订单产品 |
作为 Nexperia 的客户,您可以通过我们的销售机构订购样品。
如果您没有 Nexperia 的直接账户,我们的全球和地区分销商网络可为您提供 Nexperia 样品支持。查看官方经销商列表。
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.