双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT765-1

74AUP3G16

Low-power triple buffer

The 74AUP3G16 is a triple buffer.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78B Class II

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP3G16DC 0.8 - 3.6 CMOS ± 1.9 70 3 ultra low -40~125 VSSOP8

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AUP3G16DC 74AUP3G16DCH
(935307557125)		 Active 5A SOT765-1
VSSOP8
(SOT765-1) 		SOT765-1 SOT765-1_125

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AUP3G16DC 74AUP3G16DCH 74AUP3G16DC rohs rhf rhf
品质及可靠性免责声明

文档 (8)

文件名称 标题 类型 日期
74AUP3G16 Low-power triple buffer Data sheet 2024-04-29
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT765-1 3D model for products with SOT765-1 package Design support 2020-01-22
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
VSSOP8_SOT765-1_mk plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body Marcom graphics 2017-01-28
SOT765-1 plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body Package information 2022-06-03
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10

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模型

文件名称 标题 类型 日期
SOT765-1 3D model for products with SOT765-1 package Design support 2020-01-22

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