双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AXP1T45

1-bit dual supply translating transceiver; 3-state

The 74AXP1T45 is a single bit, dual supply transceiver with 3-state output that enables bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is required and output glitches during power supply transitions are prevented using patented circuitry. As a result glitches will not appear on the outputs for supply transitions during power-up/down between 20 mV/μs and 5.5 V/s. Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

Features and benefits

  • Wide supply voltage range:

    • VCC(A): 0.9 V to 5.5 V

    • VCC(B): 0.9 V to 5.5 V

  • Low input capacitance; CI = 1.5 pF (typical)

  • Low output capacitance; CO = 3.8 pF (typical)

  • Low dynamic power consumption; CPD = 11 pF (typical)

  • Low static power consumption; ICC = 2 μA (25 °C maximum)

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-12 (1.1 V to 1.3 V; inputs)

    • JESD8-11 (1.4 V to 1.6 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

    • JESD12-6 (4.5 V to 5.5 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Latch-up performance exceeds 100 mA per JESD78D Class II

  • Inputs accept voltages up to 5.5 V

  • Low noise overshoot and undershoot < 10% of VCCO

  • IOFF circuitry provides partial power-down mode operation

  • Specified from -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AXP1T45GW 0.9 - 5.5 0.9 - 5.5 CMOS ± 12 9 1 ultra low -40~125 TSSOP6
74AXP1T45GX 0.9 - 5.5 0.9 - 5.5 CMOS ± 12 9 1 ultra low -40~125 X2SON6

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AXP1T45GW 74AXP1T45GWH
(935690966125)		 Active R5 SOT363-2
TSSOP6
(SOT363-2) 		SOT363-2 SOT363-2_125
74AXP1T45GX 74AXP1T45GXZ
(935690967147)		 Active R5 SOT1255-2
X2SON6
(SOT1255-2) 		SOT1255-2 SOT1255-2_147

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AXP1T45GW 74AXP1T45GWH 74AXP1T45GW rohs rhf rhf
74AXP1T45GX 74AXP1T45GXZ 74AXP1T45GX rohs rhf rhf
品质及可靠性免责声明

文档 (6)

文件名称 标题 类型 日期
74AXP1T45 1-bit dual supply translating transceiver; 3-state Data sheet 2023-07-07
AN90029 Pin FMEA for AXPnT family Application note 2021-07-13
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02
SOT1255-2 3D model for products with SOT1255-2 package Design support 2021-01-28
SOT363-2 plastic thin shrink small outline package; 6 leads; body width 1.25 mm Package information 2022-11-21
SOT1255-2 plastic thermal enhanced extremely thin small outline package; no leads;6 terminals; body 1.0 x 0.8 x 0.32 mm Package information 2020-08-27

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模型

文件名称 标题 类型 日期
SOT363-2 3D model for products with SOT363-2 package Design support 2023-02-02
SOT1255-2 3D model for products with SOT1255-2 package Design support 2021-01-28

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