双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC595A

8-bit serial-in/serial-out or parallel-out shift register; 3-state

The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 1.2 V to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • CMOS low power dissipation

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Balanced propagation delays

  • All inputs have Schmitt-trigger action

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications

  • Serial-to-parallel data conversion

  • Remote control holding register

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74LVC595ABQ 1.2 - 5.5 CMOS/LVTTL ± 24 4.0 180 8 low -40~125 DHVQFN16
74LVC595AD 1.2 - 5.5 CMOS/LVTTL ± 24 4.0 180 8 low -40~125 SO16
74LVC595APW 1.2 - 5.5 CMOS/LVTTL ± 24 4.0 180 8 low -40~125 TSSOP16

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC595ABQ 74LVC595ABQ,115
(935282468115)		 Active VC595A SOT763-1
DHVQFN16
(SOT763-1) 		SOT763-1 SOT763-1_115
74LVC595AD 74LVC595AD,118
(935282469118)		 Active 74LVC595AD SOT109-1
SO16
(SOT109-1) 		SOT109-1 SO-SOJ-REFLOW
SO-SOJ-WAVE
WAVE_BG-BD-1
SOT109-1_118
74LVC595APW 74LVC595APW,118
(935282471118)		 Active LVC595A SOT403-1
TSSOP16
(SOT403-1) 		SOT403-1 SSOP-TSSOP-VSO-WAVE
SOT403-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC595ABQ 74LVC595ABQ,115 74LVC595ABQ rohs rhf rhf
74LVC595AD 74LVC595AD,118 74LVC595AD rohs rhf rhf
74LVC595APW 74LVC595APW,118 74LVC595APW rohs rhf rhf
品质及可靠性免责声明

文档 (21)

文件名称 标题 类型 日期
74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Data sheet 2024-02-22
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
mbc319 Block diagram: 74LVC595ABQ, 74LVC595AD, 74LVC595APW Block diagram 2009-11-03
mbc320 Block diagram: 74LVC595ABQ, 74LVC595AD, 74LVC595APW Block diagram 2009-11-03
mbc321 Block diagram: 74AHC594BQ, 74AHC594D, 74AHC594DB, 74AHC594PW, 74AHCT594BQ, 74AHCT594D, 74AHCT594DB, 74AHCT594PW, 74LVC595ABQ, 74LVC595AD, 74LVC595APW Block diagram 2009-11-04
SOT763-1 3D model for products with SOT763-1 package Design support 2019-10-03
SOT109-1 3D model for products with SOT109-1 package Design support 2020-01-22
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DHVQFN16_SOT763-1_mk plastic, dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 0.85 mm body Marcom graphics 2017-01-28
SO16_SOT109-1_mk plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.35 mm body Marcom graphics 2017-01-28
TSSOP16_SOT403-1_mk plastic, thin shrink small outline package; 16 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT763-1 plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 1 mm body Package information 2023-05-11
SOT109-1 plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm body Package information 2023-11-07
SOT403-1 plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-08
SO-SOJ-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SO-SOJ-WAVE Footprint for wave soldering Wave soldering 2009-10-08
WAVE_BG-BD-1 Wave soldering profile Wave soldering 2021-09-08
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
SOT763-1 3D model for products with SOT763-1 package Design support 2019-10-03
SOT109-1 3D model for products with SOT109-1 package Design support 2020-01-22
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22

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