双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT403-1

74AVC4T774PW

4-bit dual supply translating transceiver; 3-state

The 74AVC4T774PW is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 1.95 V for translating between the 0.8 V, 1.2 V, 1.5 V and 1.8 V supply voltage nodes or 1.1 V to 3.6 V for translating between the 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V supply voltage nodes. Pins An, OE and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

Features and benefits

  • Wide supply voltage range:

    • VCC(A) and VCC(B): 0.8 V to 1.95 V or 1.1 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1500 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AVC4T774PW 0.8 - 3.6 0.8 - 3.6 CMOS/LVTTL ± 12 2.1 4 very low -40~125 TSSOP16

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVC4T774PW 74AVC4T774PWJ
(935341328118)		 Active VC4T774 SOT403-1
TSSOP16
(SOT403-1) 		SOT403-1 SSOP-TSSOP-VSO-WAVE
SOT403-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVC4T774PW 74AVC4T774PWJ 74AVC4T774PW rohs rhf rhf
品质及可靠性免责声明

文档 (10)

文件名称 标题 类型 日期
74AVC4T774PW 4-bit dual supply translating transceiver; 3-state Data sheet 2024-01-29
AN90007 Pin FMEA for AVC family Application note 2018-11-30
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22
avc4t774 AVC4T774 IBIS model IBIS model 2017-10-04
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP16_SOT403-1_mk plastic, thin shrink small outline package; 16 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body Marcom graphics 2017-01-28
SOT403-1 plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm body Package information 2023-11-08
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
SOT403-1 3D model for products with SOT403-1 package Design support 2020-01-22
avc4t774 AVC4T774 IBIS model IBIS model 2017-10-04

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