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Click here for more information74AHCT2G00DP
Dual 2-input NAND gate
The 74AHC2G00; 74AHCT2G00 are high-speed Si-gate CMOS devices. They provide two 2-input NAND gates.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
Features and benefits
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
参数类型
型号 | Package name |
---|---|
74AHCT2G00DP | TSSOP8 |
封装
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74AHCT2G00DP | 74AHCT2G00DP,125 (935274679125) |
Obsolete | C00 Standard Procedure Standard Procedure |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
文档 (8)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74AHC_AHCT2G00 | Dual 2-input NAND gate | Data sheet | 2023-08-31 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11106 | Pin FMEA for AHC/AHCT family | Application note | 2019-01-09 |
Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
ahct2g00 | ahct2g00 IBIS model | IBIS model | 2013-04-08 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.