74ALVCH16652
16-bit transceiver/register with dual enable; 3-state
The 74ALVCH16652 consists of 16 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Data on the ‘A’ or ‘B’, or both buses, will be stored in the internal registers, at the appropriate clock inputs (nCPAB or nCPBA) regardless of the select inputs (nSAB and nSBA) or output enable (nOEAB and nOEBA) control inputs.
Depending on the select inputs nSAB and nSBA data can directly go from input to output (real-time mode) or data can be controlled by the clock (storage mode), when OE inputs permit this operating mode.
The output enable inputs nOEAB and nOEBA determine the operation mode of the transceiver. When nOEAB is LOW, no data transmission from nBn to nAn is possible and when nOEBA is HIGH, no data transmission from nBn to nAn is possible.
When nSAB and nSBA are in the real-time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling nOEAB and nOEBA. In this configuration each output reinforces its input.
Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features and benefits
Wide supply voltage range of 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Current drive ±24 mA at VCC = 3.0 V.
MULTIBYTE™ flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
All data inputs have bushold
Output drive capability 50 Ω transmission lines at 85 °C
Complies with JEDEC standards:
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C
参数类型
| 型号 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16652DGG | n.a. | n.a. | TTL | ± 24 | 2.6 | 16 | 150 | low | -40~85 | TSSOP56 |
封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16652DGG | 74ALVCH16652DGG,11 (935262799118) |
Active | ALVCH16652 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT364-1_118 |
下表中的所有产品型号均已停产 。
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74ALVCH16652DGG | 74ALVCH16652DGGY (935262799518) |
Discontinued / End-of-life | ALVCH16652 |
TSSOP56 (SOT364-1) |
SOT364-1 |
SSOP-TSSOP-VSO-WAVE
|
暂无信息 |
环境信息
| 型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVCH16652DGG | 74ALVCH16652DGG,11 | 74ALVCH16652DGG |
|
|
下表中的所有产品型号均已停产 。
| 型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74ALVCH16652DGG | 74ALVCH16652DGGY | 74ALVCH16652DGG |
|
|
文档 (8)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74ALVCH16652 | 16-bit transceiver/register with dual enable; 3-state | Data sheet | 2024-07-08 |
| mna319 | Block diagram: 74ALVCH16652DGG | Block diagram | 2009-11-04 |
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16652 | alvch16652 IBIS model | IBIS model | 2013-04-08 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| SOT364-1 | plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body | Package information | 2022-06-23 |
| Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| SOT364-1 | 3D model for products with SOT364-1 package | Design support | 2020-01-22 |
| alvch16652 | alvch16652 IBIS model | IBIS model | 2013-04-08 |
Ordering, pricing & availability
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