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74AVC2T245
2-bit dual supply translating transceiver with configurable voltage translation; 3-state
The 74AVC2T245 is a 2-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 1-bit transceivers or as a 2-bit transceiver. It features two 2-bit input-output ports (An and Bn) and direction control inputs (DIRn), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.
Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
Maximum data rates:
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 3.3 V translation)
200 Mbit/s (≥ 1.1 V to 2.5 V translation)
200 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
参数类型
型号 | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|---|
74AVC2T245GU | 0.8 - 3.6 | 0.8 - 3.6 | CMOS/LVTTL | ± 12 | 2.1 | 2 | very low | -40~125 | XQFN10 |
封装
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74AVC2T245GU | 74AVC2T245GUX (935308972115) |
Active | B3 |
![]() XQFN10 (SOT1160-1) |
SOT1160-1 | SOT1160-1_115 |
文档 (10)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74AVC2T245 | 2-bit dual supply translating transceiver with configurable voltage translation; 3-state | Data sheet | 2024-07-02 |
AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
Nexperia_document_guide_Logic_translators | Nexperia Logic Translators | Brochure | 2021-04-12 |
Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
SOT1160-1 | 3D model for products with SOT1160-1 package | Design support | 2019-10-03 |
avc2t245 | avc2t245 IBIS model | IBIS model | 2017-06-02 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
XQFN10_SOT1160-1_mk | plastic, extremely thin quad flat package; no leads; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
SOT1160-1 | plastic, leadless extremely thin quad flat package; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm body | Package information | 2022-06-07 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
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