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74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
Features and benefits
Wide supply voltage range from 1.2 to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
High-impedance when VCC = 0 V
Flow-through pinout architecture
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
参数类型
型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|
74LVC573ABQ | 1.2 - 3.6 | TTL | ± 24 | 3.4 | low | -40~125 | DHVQFN20 |
74LVC573AD | 1.2 - 3.6 | TTL | ± 24 | 3.4 | low | -40~125 | SO20 |
74LVC573APW | 1.2 - 3.6 | TTL | ± 24 | 3.4 | low | -40~125 | TSSOP20 |
封装
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74LVC573ABQ | 74LVC573ABQ,115 (935273507115) |
Active | LVC573A |
![]() DHVQFN20 (SOT764-1) |
SOT764-1 | SOT764-1_115 | |
74LVC573AD | 74LVC573AD,118 (935219000118) |
Active | 74LVC573AD |
![]() SO20 (SOT163-1) |
SOT163-1 |
WAVE_BG-BD-1
|
SOT163-1_118 |
74LVC573APW | 74LVC573APW,118 (935219020118) |
Active | LVC573A LVC573A Standard Procedure Standard Procedure |
![]() TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT360-1_118 |
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74LVC573ABX | 74LVC573ABXX (935300601115) |
Obsolete | LVC573A Standard procedure Standard procedure | no package information | |||
74LVC573AD | 74LVC573AD,112 (935219000112) |
Withdrawn / End-of-life | 74LVC573AD |
![]() SO20 (SOT163-1) |
SOT163-1 |
WAVE_BG-BD-1
|
暂无信息 |
74LVC573APW | 74LVC573APW,112 (935219020112) |
Withdrawn / End-of-life | LVC573A LVC573A Standard Procedure Standard Procedure |
![]() TSSOP20 (SOT360-1) |
SOT360-1 |
SSOP-TSSOP-VSO-WAVE
|
暂无信息 |
环境信息
型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74LVC573ABQ | 74LVC573ABQ,115 | 74LVC573ABQ |
|
![]() |
74LVC573AD | 74LVC573AD,118 | 74LVC573AD |
|
![]() |
74LVC573APW | 74LVC573APW,118 | 74LVC573APW |
|
![]() |
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74LVC573ABX | 74LVC573ABXX | 74LVC573ABX |
|
![]() |
74LVC573AD | 74LVC573AD,112 | 74LVC573AD |
|
![]() |
74LVC573APW | 74LVC573APW,112 | 74LVC573APW |
|
![]() |
文档 (17)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74LVC573A | Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state | Data sheet | 2023-09-07 |
AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
AN263 | Power considerations when using CMOS and BiCMOS logic devices | Application note | 2023-02-07 |
SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
lvc573a | lvc573a IBIS model | IBIS model | 2013-04-09 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
DHVQFN20_SOT764-1_mk | plastic, dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 2.5 mm x 4.5 mm x 0.85 mm body | Marcom graphics | 2017-01-28 |
TSSOP20_SOT360-1_mk | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
SOT764-1 | plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm body | Package information | 2022-06-21 |
SOT163-1 | plastic, small outline package; 20 leads; 1.27 mm pitch; 12.8 mm x 7.5 mm x 2.65 mm body | Package information | 2022-06-20 |
SOT360-1 | plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm body | Package information | 2022-06-21 |
lvc | lvc Spice model | SPICE model | 2013-05-07 |
Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
支持
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模型
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
SOT764-1 | 3D model for products with SOT764-1 package | Design support | 2019-10-03 |
SOT163-1 | 3D model for products with SOT163-1 package | Design support | 2020-01-22 |
SOT360-1 | 3D model for products with SOT360-1 package | Design support | 2020-01-22 |
lvc573a | lvc573a IBIS model | IBIS model | 2013-04-09 |
lvc | lvc Spice model | SPICE model | 2013-05-07 |
Ordering, pricing & availability
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