74ALVCH16501DGG

18-bit universal bus transceiver; 3-state

The 74ALVCH16501 is an 18-bit universal transceiver with bus hold inputs and 3-state outputs. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH and OEBA is active LOW). This device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
Direct interface with TTL levels
Current drive ±24 mA at V_CC = 3.0 V
Universal bus transceiver with D-type latches and D-type flip-flops capable of operating in transparent, latched or clocked mode
Bus hold on all data inputs
Output drive capability 50 Ω transmission lines at 85 °C
3-state non-inverting outputs for bus-oriented applications
Latch-up performance exceeds 100 mA per JESD78 Class II.A
Complies with JEDEC standards:
- JESD8-7 (1.65 V to 1.95 V)
- JESD8-5 (2.3 V to 2.7 V)
- JESD8C/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C

参数类型

型号	V_CC(A) (V)	V_CC(B) (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	Nr of bits	f_max (MHz)	Power dissipation considerations	T_amb (°C)	Package name
74ALVCH16501DGG	n.a.	n.a.	TTL	± 24	2.8	18	150	low	-40~85	TSSOP56

封装

型号	可订购的器件编号，（订购码(12NC)）	状态	标示	封装	外形图	回流焊/波峰焊	包装
74ALVCH16501DGG	74ALVCH16501DGG,11 (935262543118)	Active	ALVCH16501	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	SOT364-1_118

下表中的所有产品型号均已停产。

型号	可订购的器件编号，（订购码(12NC)）	状态	标示	封装	外形图	回流焊/波峰焊	包装
74ALVCH16501DGG	74ALVCH16501DGGY (935262543518)	Withdrawn / End-of-life	ALVCH16501	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	暂无信息

环境信息

型号	可订购的器件编号	化学成分	RoHS	RHF指示符
74ALVCH16501DGG	74ALVCH16501DGG,11	74ALVCH16501DGG

下表中的所有产品型号均已停产。

型号	可订购的器件编号	化学成分	RoHS	RHF指示符
74ALVCH16501DGG	74ALVCH16501DGGY	74ALVCH16501DGG

品质及可靠性免责声明

Series

文档 (8)

文件名称	标题	类型	日期
74ALVCH16501	18-bit universal bus transceiver; 3-state	Data sheet	2024-07-01
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22
alvch16501	alvch16501 IBIS model	IBIS model	2013-04-08
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
SOT364-1	plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body	Package information	2022-06-23
SOT364-1_118	TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation	Packing information	2020-04-21
74ALVCH16501DGG_Nexperia_Product_Reliability	74ALVCH16501DGG Nexperia Product Reliability	Quality document	2024-06-16
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08

支持

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模型

文件名称	标题	类型	日期
alvch16501	alvch16501 IBIS model	IBIS model	2013-04-08
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22

订购、定价与供货

型号	Orderable part number	Ordering code (12NC)	状态	包装	Packing Quantity	在线购买
74ALVCH16501DGG	74ALVCH16501DGG,11	935262543118	Active	SOT364-1_118	2,000	订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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