74ALVCH16823DGG

18-bit bus-interface D-type flip-flop with reset and enable; 3-state

The 74ALVCH16823 is an 18-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. Incorporates bushold data inputs which eliminate the need for external pull-up resistors to hold unused inputs. The 74ALVCH16823 consists of two sections of nine edge-triggered flip-flops. A clock (nCP) input, an output-enable (nOE) input, a master reset (nMR) input and a clock-enable (nCE) input are provided for each total 9-bit section.

With the clock-enable (nCE) input LOW, the D-type flip-flops will store the state of their individual nDn-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH nCP transition. Taking nCE HIGH disables the clock buffer, thus latching the outputs. Taking the master reset (nMR) input LOW causes all the nQn outputs to go LOW independently of the clock.

When nOE is LOW, the contents of the flip-flops are available at the outputs. When the nOE is HIGH, the outputs go to the high impedance OFF-state. Operation of the nOE input does not affect the state of flip-flops.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features and benefits

Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Current drive ± 24 mA at 3.0 V
MULTIBYTE™ flow-through standard pin-out architecture
Low inductance multiple V_CC and GND pins for minimum noise and ground bounce
Output drive capability 50 Ω transmission lines at 85°C
All data inputs have bushold
Complies with JEDEC standard no. 8-1A
Complies with JEDEC standards:
- JESD8-5 (2.3 V to 2.7 V)
- JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C

参数类型

型号	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	Package name
74ALVCH16823DGG	1.2 - 3.6	TTL	± 24	2.1	350	low	-40~85	TSSOP56

封装

型号	可订购的器件编号，（订购码(12NC)）	状态	标示	封装	外形图	回流焊/波峰焊	包装
74ALVCH16823DGG	74ALVCH16823DGG,11 (935259030118)	Active	ALVCH16823	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	SOT364-1_118

下表中的所有产品型号均已停产。

型号	可订购的器件编号，（订购码(12NC)）	状态	标示	封装	外形图	回流焊/波峰焊	包装
74ALVCH16823DGG	74ALVCH16823DGGS (935259030512)	Withdrawn / End-of-life	ALVCH16823	TSSOP56 (SOT364-1)	SOT364-1	SSOP-TSSOP-VSO-WAVE	暂无信息

环境信息

型号	可订购的器件编号	化学成分	RoHS	RHF指示符
74ALVCH16823DGG	74ALVCH16823DGG,11	74ALVCH16823DGG

下表中的所有产品型号均已停产。

型号	可订购的器件编号	化学成分	RoHS	RHF指示符
74ALVCH16823DGG	74ALVCH16823DGGS	74ALVCH16823DGG

品质及可靠性免责声明

Series

文档 (8)

文件名称	标题	类型	日期
74ALVCH16823	18-bit bus-interface D-type flip-flop with reset and enable; 3-state	Data sheet	2024-07-09
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22
alvch16823	alvch16823 IBIS model	IBIS model	2013-04-08
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
SOT364-1	plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body	Package information	2022-06-23
SOT364-1_118	TSSOP56; Reel pack for SMD, 13"; Q1/T1 product orientation	Packing information	2020-04-21
74ALVCH16823DGG_Nexperia_Product_Reliability	74ALVCH16823DGG Nexperia Product Reliability	Quality document	2024-06-16
SSOP-TSSOP-VSO-WAVE	Footprint for wave soldering	Wave soldering	2009-10-08

支持

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模型

文件名称	标题	类型	日期
alvch16823	alvch16823 IBIS model	IBIS model	2013-04-08
SOT364-1	3D model for products with SOT364-1 package	Design support	2020-01-22

订购、定价与供货

型号	Orderable part number	Ordering code (12NC)	状态	包装	Packing Quantity	在线购买
74ALVCH16823DGG	74ALVCH16823DGG,11	935259030118	Active	SOT364-1_118	2,000	订单产品

样品

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