74LVC1G53-Q100
2-channel analog multiplexer/demultiplexer
The 74LVC1G53-Q100 is a single-pole double-throw analog switch with a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and a digital enable input (E). When E is HIGH, the switch is turned off. Control inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at control inputs makes the circuit tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
Very low ON resistance:
7.5 Ω (typical) at VCC = 2.7 V
6.5 Ω (typical) at VCC = 3.3 V
6 Ω (typical) at VCC = 5 V
Switch current capability of 32 mA
High noise immunity
CMOS low power consumption
TTL interface compatibility at 3.3 V
Latch-up performance meets requirements of JESD 78 Class I
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
参数类型
| 型号 | Configuration | VCC (V) | RON (Ω) | Logic switching levels | Power dissipation considerations | Tamb (°C) | Package name |
|---|---|---|---|---|---|---|---|
| 74LVC1G53DC-Q100 | SPDT-Z | 1.65 - 5.5 | 15 | CMOS/LVTTL | very low | -40~125 | VSSOP8 |
| 74LVC1G53DP-Q100 | SPDT-Z | 1.65 - 5.5 | 15 | CMOS/LVTTL | very low | -40~125 | TSSOP8 |
封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74LVC1G53DC-Q100 | 74LVC1G53DC-Q100H (935300246125) |
Active | V53 |
VSSOP8 (SOT765-1) |
SOT765-1 | SOT765-1_125 | |
| 74LVC1G53DP-Q100 | 74LVC1G53DP-Q100H (935300247125) |
Active | V53 |
TSSOP8 (SOT505-2) |
SOT505-2 | SOT505-2_125 |
环境信息
| 型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
|---|---|---|---|---|
| 74LVC1G53DC-Q100 | 74LVC1G53DC-Q100H | 74LVC1G53DC-Q100 |
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| 74LVC1G53DP-Q100 | 74LVC1G53DP-Q100H | 74LVC1G53DP-Q100 |
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文档 (12)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74LVC1G53_Q100 | 2-channel analog multiplexer/demultiplexer | Data sheet | 2023-08-24 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11009 | Pin FMEA for LVC family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_PicoGate_201901 | PicoGate leaded logic portfolio guide | Brochure | 2019-01-07 |
| SOT765-1 | 3D model for products with SOT765-1 package | Design support | 2020-01-22 |
| SOT505-2 | 3D model for products with SOT505-2 package | Design support | 2019-01-18 |
| lvc1g53 | 74LVC1G53 IBIS model | IBIS model | 2015-02-19 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| VSSOP8_SOT765-1_mk | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Marcom graphics | 2017-01-28 |
| SOT765-1 | plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body | Package information | 2022-06-03 |
| SOT505-2 | plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body | Package information | 2022-06-03 |
| Nexperia_Selection_guide_2023 | Nexperia Selection Guide 2023 | Selection guide | 2023-05-10 |
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