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74HC107-Q100; 74HCT107-Q100
Dual JK flip-flop with reset; negative-edge trigger
The 74HC107-Q100; 74HCT107-Q100 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
Input levels:
For 74HC107-Q100: CMOS level
For 74HCT107-Q100: TTL level
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
参数类型
型号 | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Package name |
---|---|---|---|---|---|---|---|---|
74HC107D-Q100 | 2.0 - 6.0 | CMOS | ± 5.2 | 16 | 78 | low | -40~125 | SO14 |
74HC107PW-Q100 | 2.0 - 6.0 | CMOS | ± 5.2 | 16 | 78 | low | -40~125 | TSSOP14 |
74HCT107D-Q100 | 4.5 - 5.5 | TTL | ± 4 | 16 | 73 | low | -40~125 | SO14 |
封装
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74HC107D-Q100 | 74HC107D-Q100J (935302252118) |
Active | 74HC107D |
![]() SO14 (SOT108-1) |
SOT108-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT108-1_118 |
74HC107PW-Q100 | 74HC107PW-Q100J (935302253118) |
Active | HC107 |
![]() TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
74HCT107D-Q100 | 74HCT107D-Q100J (935302254118) |
Active | 74HCT107D |
![]() SO14 (SOT108-1) |
SOT108-1 |
SO-SOJ-REFLOW
SO-SOJ-WAVE WAVE_BG-BD-1 |
SOT108-1_118 |
环境信息
型号 | 可订购的器件编号 | 化学成分 | RoHS | RHF指示符 |
---|---|---|---|---|
74HC107D-Q100 | 74HC107D-Q100J | 74HC107D-Q100 |
|
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74HC107PW-Q100 | 74HC107PW-Q100J | 74HC107PW-Q100 |
|
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74HCT107D-Q100 | 74HCT107D-Q100J | 74HCT107D-Q100 |
|
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文档 (14)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74HC_HCT107_Q100 | Dual JK flip-flop with reset; negative-edge trigger | Data sheet | 2024-02-20 |
AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
SOT108-1 | 3D model for products with SOT108-1 package | Design support | 2020-01-22 |
SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
SO14_SOT108-1_mk | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Marcom graphics | 2017-01-28 |
TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
SOT108-1 | plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm body | Package information | 2023-11-07 |
SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
SO-SOJ-REFLOW | Footprint for reflow soldering | Reflow soldering | 2009-10-08 |
HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
SO-SOJ-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
WAVE_BG-BD-1 | Wave soldering profile | Wave soldering | 2021-09-08 |
SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
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