双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AUP2G98

Low-power dual PCB configurable multiple function gate

The 74AUP2G98 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AUP2G98DP 0.8 - 3.6 CMOS ± 1.9 8.9 70 2 ultra low -40~125 TSSOP10
74AUP2G98GU 0.8 - 3.6 CMOS ± 1.9 8.9 70 2 ultra low -40~125 XQFN10

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AUP2G98DP 74AUP2G98DPJ
(935304485118)		 Active a9 SOT552-1
TSSOP10
(SOT552-1) 		SOT552-1 SSOP-TSSOP-VSO-WAVE
SOT552-1_118
74AUP2G98GU 74AUP2G98GUX
(935304488115)		 Active a9 SOT1160-1
XQFN10
(SOT1160-1) 		SOT1160-1 SOT1160-1_115

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AUP2G98DP 74AUP2G98DPJ 74AUP2G98DP rohs rhf rhf
74AUP2G98GU 74AUP2G98GUX 74AUP2G98GU rohs rhf rhf
品质及可靠性免责声明

文档 (13)

文件名称 标题 类型 日期
74AUP2G98 Low-power dual PCB configurable multiple function gate Data sheet 2023-07-31
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT552-1 3D model for products with SOT552-1 package Design support 2020-01-22
SOT1160-1 3D model for products with SOT1160-1 package Design support 2019-10-03
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP10_SOT552_mk plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body Marcom graphics 2017-01-28
XQFN10_SOT1160-1_mk plastic, extremely thin quad flat package; no leads; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT552-1 plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm body Package information 2022-06-07
SOT1160-1 plastic, leadless extremely thin quad flat package; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm body Package information 2022-06-07
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

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模型

文件名称 标题 类型 日期
SOT552-1 3D model for products with SOT552-1 package Design support 2020-01-22
SOT1160-1 3D model for products with SOT1160-1 package Design support 2019-10-03

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