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Click here for more information74HC2G86GD
Dual 2-input EXCLUSIVE-OR gate
The 74HC2G86; 74HCT2G86 is a dual 2-input EXCLUSIVE-OR gate. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Alternatives
Features and benefits
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Input levels:
For 74HC2G86: CMOS level
For 74HCT2G86: TTL level
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
参数类型
型号 | Package name |
---|---|
74HC2G86GD | XSON8 |
封装
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74HC2G86GD | 74HC2G86GD,125 (935288582125) |
Obsolete | H86 Standard Procedure Standard Procedure |
XSON8 (SOT996-2) |
SOT996-2 | SOT996-2_125 |
文档 (5)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74HC_HCT2G86 | Dual 2-input EXCLUSIVE-OR gate | Data sheet | 2023-11-28 |
AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
SOT996-2 | plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 3 mm x 2 mm x 0.5 mm body | Package information | 2020-04-21 |
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模型
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.