双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVCH16373ADGG-Q100

16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Bus hold on the data inputs eliminates the need for external pull-up resistors to hold unused inputs.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Overvoltage tolerant inputs to 5.5 V

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power dissipation

  • MULTIBYTE flow-through standard pinout architecture

  • Multiple low inductance supply pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold (74LVCH16373A-Q100 only)

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standards:
    • JESD8-7A (1.65 V to 1.95 V)
    • JESD8-5A (2.3 V to 2.7 V)
    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

型号 VCC (V) Logic switching levels Output drive capability (mA) tpd (ns) Power dissipation considerations Tamb (°C) Package name
74LVCH16373ADGG-Q100 1.2 - 3.6 TTL ± 24 3 low -40~125 TSSOP48

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVCH16373ADGG-Q100 74LVCH16373ADGG-QJ
(935304872118)		 Active LVCH16373A SOT362-1
TSSOP48
(SOT362-1) 		SOT362-1 SSOP-TSSOP-VSO-WAVE
SOT362-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVCH16373ADGG-Q100 74LVCH16373ADGG-QJ 74LVCH16373ADGG-Q100 rohs rhf rhf
品质及可靠性免责声明

Series

文档 (11)

文件名称 标题 类型 日期
74LVC_LVCH16373A_Q100 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Data sheet 2024-04-23
AN11009 Pin FMEA for LVC family Application note 2019-01-09
AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP48_SOT362-1_mk plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body Marcom graphics 2017-01-28
SOT362-1 plastic thin shrink small outline package; 48 leads; body width 6.1 mm Package information 2024-01-05
SOT362-1_118 TSSOP48; Reel pack for SMD, 13''; Q1/T1 product orientation Packing information 2020-04-21
74LVCH16373ADGG-Q100_Nexperia_Product_Reliability 74LVCH16373ADGG-Q100 Nexperia Product Reliability Quality document 2024-06-16
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

模型

文件名称 标题 类型 日期
lvch16373a lvch16373a IBIS model IBIS model 2013-04-09
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22

PCB Symbol, Footprint and 3D Model

Model Name 描述

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74LVCH16373ADGG-Q100 74LVCH16373ADGG-QJ 935304872118 Active SOT362-1_118 2,000 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

交互式数据手册

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVCH16373ADGG-Q100 74LVCH16373ADGG-QJ 935304872118 SOT362-1 订单产品