双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT362-1

74AVCH16T245

16-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVCH16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (VCC(A) and VCC(B)) for voltage translation and four 8-bit input-output ports (nAn, nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B outputs are in the high-impedance OFF-state. The bus-hold circuitry on the powered-up side always stays active.

The 74AVCH16T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features and benefits

  • Wide supply voltage range: VCC(A): 0.8 V to 3.6 V and VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Bus hold on data inputs

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AVCH16T245DGG 0.8 - 3.6 0.8 - 3.6 CMOS/LVTTL ± 12 2.1 16 very low -40~125 TSSOP48

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVCH16T245DGG 74AVCH16T245DGG,18
(935286233118)		 Active AVCH16T245 SOT362-1
TSSOP48
(SOT362-1) 		SOT362-1 SSOP-TSSOP-VSO-WAVE
SOT362-1_118

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVCH16T245BX 74AVCH16T245BX,518
(935295868518)		 Obsolete AVCH16T245 Standard Procedure Standard Procedure no package information
74AVCH16T245EV 74AVCH16T245EV,518
(935288139518)		 Obsolete AVCH16T245 Standard Procedure Standard Procedure no package information
74AVCH16T245EV,551
(935288139551)		 Obsolete AVCH16T245 Standard Procedure Standard Procedure
74AVCH16T245EV,557
(935288139557)		 Obsolete AVCH16T245 Standard Procedure Standard Procedure

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVCH16T245DGG 74AVCH16T245DGG,18 74AVCH16T245DGG rohs rhf rhf

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVCH16T245BX 74AVCH16T245BX,518 74AVCH16T245BX rohs rhf rhf
74AVCH16T245EV 74AVCH16T245EV,518 74AVCH16T245EV rhf
74AVCH16T245EV 74AVCH16T245EV,551 74AVCH16T245EV rhf
74AVCH16T245EV 74AVCH16T245EV,557 74AVCH16T245EV rhf
品质及可靠性免责声明

文档 (9)

文件名称 标题 类型 日期
74AVCH16T245 16-bit dual supply translating transceiver with configurable voltage translation; 3-state Data sheet 2024-06-25
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22
avch16t245 74AVCH16T245 Ibis model IBIS model 2014-10-14
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
TSSOP48_SOT362-1_mk plastic, thin shrink small outline package; 48 leads; 0.5 mm pitch; 12.8 mm x 6.1 mm x 1.2 mm body Marcom graphics 2017-01-28
SOT362-1 plastic thin shrink small outline package; 48 leads; body width 6.1 mm Package information 2024-01-05
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
SOT362-1 3D model for products with SOT362-1 package Design support 2020-01-22
avch16t245 74AVCH16T245 Ibis model IBIS model 2014-10-14

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