双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)
SOT364-1

74AVCH20T245

20-bit dual supply translating transceiver with configurable voltage translation; 3-state

The 74AVCH20T245 is a 20-bit, dual supply transceiver that enables bi-directional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn and 2An, 2Bn), two output enable inputs (nOE), two direction inputs (nDIR) and dual supplies (VCC(A) and VCC(B)). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V making the device suitable for bi-directional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE and nDIR are referenced to VCC(A), the 1Bn and 2Bn ports are referenced to VCC(B). A HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH impedance OFF-state.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all output ports will assume a high impedance OFF-state. The bus hold circuitry on the powered-up side always stays active.

The 74AVCH20T245 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

Features and benefits

  • Wide supply voltage range: VCC(A): 0.8 V to 3.6 V; VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 260 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 260 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 210 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 120 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Bus hold on data inputs

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

型号 VCC(A) (V) VCC(B) (V) Logic switching levels Output drive capability (mA) tpd (ns) Nr of bits Power dissipation considerations Tamb (°C) Package name
74AVCH20T245DGG 0.8 - 3.6 0.8 - 3.6 CMOS/LVTTL ± 12 2.1 20 very low -40~125 TSSOP56

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74AVCH20T245DGG 74AVCH20T245DGG,11
(935286236118)		 Active AVCH20T245 SOT364-1
TSSOP56
(SOT364-1) 		SOT364-1 SSOP-TSSOP-VSO-WAVE
SOT364-1_118

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74AVCH20T245DGG 74AVCH20T245DGG,11 74AVCH20T245DGG rohs rhf rhf
品质及可靠性免责声明

文档 (7)

文件名称 标题 类型 日期
74AVCH20T245 20-bit dual supply translating transceiver with configurable voltage translation; 3-state Data sheet 2024-06-25
Nexperia_document_guide_Logic_translators Nexperia Logic Translators Brochure 2021-04-12
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT364-1 plastic, thin shrink small outline package; 56 leads; 0.5 mm pitch; 14 mm x 6.1 mm x 1.2 mm body Package information 2022-06-23
Nexperia_Selection_guide_2023 Nexperia Selection Guide 2023 Selection guide 2023-05-10
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

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模型

文件名称 标题 类型 日期
SOT364-1 3D model for products with SOT364-1 package Design support 2020-01-22

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