双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74AUP1G07GF

Low-power buffer with open-drain output

The 74AUP1G07 is a single buffer with open-drain output.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

Not recommended for new designs (NRND).

Alternatives

Features and benefits

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • CMOS low power dissipation

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8C (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Overvoltage tolerant inputs to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Multiple package options

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

Parametrics

Type number Package name
74AUP1G07GF
XSON6

PCB Symbol, Footprint and 3D Model

Model Name Description

Series

Documentation (12)

File name Title Type Date
74AUP1G07 Low-power buffer with open-drain output Data sheet 2024-08-30
AN10161 PicoGate Logic footprints Application note 2002-10-29
AN11052 Pin FMEA for AUP family Application note 2019-01-09
Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
SOT891 3D model for products with SOT891 package Design support 2019-10-03
aup1g07 74AUP1G07 IBIS model IBIS model 2014-12-14
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 Leaflet 2019-04-12
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
DFN1010-6_SOT891_mk plastic, extremely thin small outline package; 6 terminals; 0.55 mm pitch; 1 mm x 1 mm x 0.5 mm body Marcom graphics 2017-01-28
SOT891 plastic, leadless extremely thin small outline package; 6 terminals; 0.35 mm pitch; 1 mm x 1 mm x 0.5 mm body Package information 2020-04-21
REFLOW_BG-BD-1 Reflow soldering profile Reflow soldering 2021-04-06
MAR_SOT891 MAR_SOT891 Topmark Top marking 2013-06-03

Support

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Models

File name Title Type Date
aup1g07 74AUP1G07 IBIS model IBIS model 2014-12-14
SOT891 3D model for products with SOT891 package Design support 2019-10-03

PCB Symbol, Footprint and 3D Model

Model Name Description

Ordering, pricing & availability

Sample

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If you do not have a direct account with Nexperia our network of global and regional distributors is available and equipped to support you with Nexperia samples. Check out the list of official distributors.

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

Interactive datasheet