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Click here for more information74AUP2G80GM
Low-power dual D-type flip-flop; positive-edge trigger
The 74AUP2G80 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.
Alternatives
Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C
Parametrics
| Type number | Package name |
|---|---|
| 74AUP2G80GM | XQFN8 |
PCB Symbol, Footprint and 3D Model
| Model Name | Description |
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Package
All type numbers in the table below are discontinued.
| Type number | Orderable part number, (Ordering code (12NC)) | Status | Marking | Package | Package information | Reflow-/Wave soldering | Packing |
|---|---|---|---|---|---|---|---|
| 74AUP2G80GM | 74AUP2G80GM,125 (935281429125) |
Withdrawn / End-of-life | p80 |
XQFN8 (SOT902-2) |
SOT902-2 | SOT902-2_125 |
Environmental information
All type numbers in the table below are discontinued.
| Type number | Orderable part number | Chemical content | RoHS | RHF-indicator |
|---|---|---|---|---|
| 74AUP2G80GM | 74AUP2G80GM,125 | 74AUP2G80GM |
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Series
Documentation (9)
| File name | Title | Type | Date |
|---|---|---|---|
| 74AUP2G80 | Low-power dual D-type flip-flop; positive-edge trigger | Data sheet | 2023-07-21 |
| AN10161 | PicoGate Logic footprints | Application note | 2002-10-29 |
| AN11052 | Pin FMEA for AUP family | Application note | 2019-01-09 |
| Nexperia_document_guide_MiniLogic_MicroPak_201808 | MicroPak leadless logic portfolio guide | Brochure | 2018-09-03 |
| aup2g80 | aup2g80 IBIS model | IBIS model | 2013-04-07 |
| Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904 | Leaflet | 2019-04-12 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| XQFN8_SOT902-2_mk | plastic, extremely thin quad flat package; 8 terminals; 0.55 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Marcom graphics | 2017-01-28 |
| SOT902-2 | plastic, leadless extremely thin quad flat package; 8 terminals; 0.5 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body | Package information | 2020-04-21 |
Support
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Models
| File name | Title | Type | Date |
|---|---|---|---|
| aup2g80 | aup2g80 IBIS model | IBIS model | 2013-04-07 |
PCB Symbol, Footprint and 3D Model
| Model Name | Description |
|---|---|
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74AUP2G80GM
Low-power dual D-type flip-flop; positive-edge trigger
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